Speed up design and verification with a smaller layout
How to remove or extract portions of a layout for easier, more focused and faster project delivery.
IC Implementation
Why hyperlinks are essential for HDL debugging
Text editors have major debug limitations that the use of hyperlinks in integrated development environments help you overcome.
High-level synthesis for AI: Part Two
How Chips&Media used HLS on the development of a computer vision IP block.
High-level synthesis for AI: Part One
The computational and algorithmic demands made by computer vision systems highlight HLS' value for AI system development.
Emulation for AI: Part Two
The second part of this feature looks at how Wave Computing's objectives with its dataflow processing unit for AI mapped to the use of emulation in its development.
Emulation for AI: Part One
An increasing number of AI players are building their own silicon and finding that emulation is key to overcoming the major challenges.
A better way to manage error reporting at the chip and block levels
In a continuous-build design flow, at which level should your error markers be addressed?
Adding system-level, post-layout electrical analysis to HDAP design and verification
Adoption of high-density advanced packaging (HDAP) needs tools and supports to build designers' confidence in the emerging technology.
Power analysis isn’t just for battery-operated products
Andy Ladd highlights the wide range of peak-power concerns around plugged-in devices.
Layout-database file control: the missing link
The authors descirbe a new signature-based approach to resolving the content of layouts in GDSII, OASIS and other formats.
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