Aim for power first for best place-and-route results
The strategy of designing for best power rather than for best timing in place-and-route delivers better results all around.
IC Implementation
Assure diagnostic coverage from RTL to gate level during analysis for functional safety
Generating accurate ASIL metrics early in the functional safety lifecycle, reduces time-to-certification for ISO26262.
Siemens’ Sawicki puts priority on scaling in processes, productivity and systems
More optimistic about the semiconductor industries prospects than for some time, Siemens Joe Sawicki identified key EDA challenges at DAC.
How to optimize productivity and accuracy in IC design and verification flows
Pre- and post-processing EDA techniques help streamline design rule checks and delivery efficient waivers to speed design and debug.
How UPMEM ensured effective power delivery for its processor-in-memory design
PIM memory boosts efficiency by operating on data without moving it to the CPU but realizing this type of novel technology posed power integration and planning challenges.
Advanced symmetry verification is a thing of beauty
Innovation is extending the technique's power across areas such as context-aware layout, accounting for multi-patterning and implementing fill.
Hit your tapeout schedules with in-design signoff DRC
Delivering physical implementations at new process nodes is getting ever harder. Learn how to stay on track by checking work is rule-compliant as you go.
Out-of-sync data issues in parallel design flows need automated design integrity checks
Overcome problems created by mismatches between library exchange format (LEF) and GDS or OASIS representations to avoid design delays.
How you can decide what level of DRC you need when you need it
Using on-demand rule checks during place-and-route boosts efficiency and design quality.
DVCon Europe best paper assesses clock design
The best paper at DVCon Europe 2020 analyzed different multiclock strategies for SoCs for their power and flexibility
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