December 22, 2017
In-design DRC is a technique that frees up engineers from many of the challenges of delivering AMS design under ever more complex design rules.
November 24, 2017
John Ferguson reviews the key capital metrics you need to review when deciding whether to move to a new process.
October 14, 2017
The assumption has been that extra security eats into profit margins. But with some lateral thinking it can actually improve the bottom line.
September 14, 2017
An alphabet soup of AI, HPC, 5G and the IoT has finally seeded creation of a design infrastructure for silicon photonics.
September 8, 2017
High level synthesis (HLS) was adopted to realize innovative display IP as developed by a small core engineering team.
May 8, 2017
Our extended fireside chat with Mentor Chairman and CEO Wally Rhines begins by canvassing his thoughts now the Siemens deal is done.
March 15, 2017
DVCon China general chair Andy Liu discusses Accellera’s new addition to its design and verification conference series (简体中文).
January 27, 2017
Richard Pugh looks at how innovations highlighted during the recent International Memory Workshop are driving the solid state drive (SSD) market.
December 9, 2016
Traditional techniques are being challenged by shortening design cycles and the effects of later process nodes.
December 2, 2016
Hierarchical signoff strategies for large SoCs at advanced nodes can be effective if sufficient attention is paid to reflecting the impact of cross-hierarchy parasitics.