July 20, 2015
In sessions at the 2015 Design Automation Conference, engineers who had worked on finFET-oriented projects revealed how the technology has changed their design practices and where others may want to think twice about making the move.
May 30, 2015
Clock-tree generation is coming under increased scrutiny because of its role in dynamic power consumption and problems caused by on-chip PVT variation.
May 28, 2015
FinFETs present a number of problems with respect to dynamic power consumption. Design techniques are being re-evaluated to deal with the issue.
April 30, 2015
Emulation is now served by all three leading vendors and is a hot topic for discussion among engineers. The major verification conferences need to follow suit.
February 3, 2015
Designers working on automotive ICs, to be built on established processes, can benefit from the power of design tools developed for advanced processes.
January 26, 2015
Precise curved geometries are vital to making this emerging and cost-effective CMOS-based technology work. This primer explains its advantages and how litho tools are evolving to meet the challenges it presents.
January 20, 2015
Combining assertion-based verification techniques with emulation makes for easier debug, better coverage and greater functional efficiency.
October 31, 2014
A look under the hood of IC Compiler II, Synopsys' next-generation netlist-to-GDSII implementation system.
October 18, 2014
Soft blocking to prevent cell spreading and other placement-optimization techniques helped improve power and clock speed on a Cortex-M7 test chip designed by ARM and Cadence.
October 6, 2014
ARM and TSMC used an extensive pre-planning process, including a static analysis of each module's overall logic structure, to put together a 2.3GHz processor design based around ARM's main 64bit Big.Little pairing for the foundry's 16nm finFET process.
