place and route

March 9, 2018
Saunder Peng is a Senior Application Engineer with Mentor, a Siemens Business. He received his B.S degree in Electrical Engineering from the University of California at Los Angeles, and his M.S. in Electrical Engineering from Columbia University, New York.

A better way to merge design files for physical verification

Still using custom layout or place and route tools here? Ditch that time-consuming practice for a real database merge flow.
October 3, 2016
Place and route beyond 10nm

How place and route is adapting to challenges below 10nm

Multi-patterning, finFETs and more are forcing more detailed overhauls of P&R software at each process node. We dig into some of the key new issues and how they are being addressed.
October 18, 2014
Soft-blocked floorplan

Placement optimizations push power and clock on Cortex-M7 project

Soft blocking to prevent cell spreading and other placement-optimization techniques helped improve power and clock speed on a Cortex-M7 test chip designed by ARM and Cadence.
September 24, 2013
TDF- Synopsys - BULL - feat

Accelerating process migration in advanced ASIC design at Bull

How the HPC company used Synopsys' Lynx Design System to standardise its flow and simplify migration to the next node.
Article  |  Topics: IP - Design Management, EDA - IC Implementation  |  Tags: , , ,   |  Organizations: ,
October 23, 2012

Vivado, inside the new Xilinx design suite

The FPGA vendor's new flagship is now on public release. It adds an array of features, including support for system-level to HDL synthesis.
October 11, 2012
Tong Gao

The physical design challenges of 20nm processes

Manufacturability, routing, library design and more - it all needs rethinking at 20nm, writes Tong Gao of Synopsys.
Expert Insight  |  Topics: EDA - DFM  |  Tags: , , , ,   |  Organizations:
September 12, 2012

Critical tools for 20nm design

A look at the way in which key tools, in IC implementation, modeling and extraction, and physical verification, are developing in response to the challenges of 20nm design
June 1, 2010

Signoff-driven IC design

The demands of manufacturing closure at advanced process nodes make the traditional design-then-fix flow unmanageable. At 28nm and below, designers need a solution that can address manufacturing issues at any point in the design process, enabling a true correct-by-construction methodology. An effective solution must provide design-rule-check and design-for-manufacturing analysis using the actual foundry-approved signoff rules [...]
Article  |  Topics: EDA - DFM  |  Tags: , , ,
April 14, 2010

Top-level MCMM closure for a multi-million-gate design

STMicroelectronics in Greater Noida, India recently completed an Omega2 set-top-box decoder IC targeted at HDTV markets. This article discusses how ST used Mentor Graphics’ Olympus-SoC software to address the closure challenges presented by a very large design. It describes how the design team used the tool suite’s chip assembly, concurrent multi-corner multi-mode (MCMM) analysis and [...]
Article  |  Topics: EDA - DFM  |  Tags: , ,
May 1, 2009

The art of low-power physical design

The architectures that underpin today’s traditional place-and-route tools are showing their age, largely because their static timing analysis engines cannot handle more than two mode/corner scenarios. Thus limited, the software struggles to effectively implement low-power design techniques beyond such established concepts as clock gating and multiple threshold voltages. Designers run into difficulties when trying to […]

Article  |  Topics: EDA - DFM  |  Tags: , , ,


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