place and route

October 3, 2016
Place and route beyond 10nm

How place and route is adapting to challenges below 10nm

Multi-patterning, finFETs and more are forcing more detailed overhauls of P&R software at each process node. We dig into some of the key new issues and how they are being addressed.
October 18, 2014
Soft-blocked floorplan

Placement optimizations push power and clock on Cortex-M7 project

Soft blocking to prevent cell spreading and other placement-optimization techniques helped improve power and clock speed on a Cortex-M7 test chip designed by ARM and Cadence.
January 13, 2014
Interconnect resistance has increased since the 40nm node

Interconnect resistance

A number of effects have led to a dramatic increase in interconnect resistance in the sub-32nm process nodes that demands the use of smarter routing.
January 13, 2014
Multiple patterning is causing issues with access to standard-cell pins in nanometer processes

Cell pin access

Increasingly complex design rules in 14nm and 16nm make it harder to connect local routing to the inputs and outputs (pins) of standard cells.
September 24, 2013
TDF- Synopsys - BULL - feat

Accelerating process migration in advanced ASIC design at Bull

How the HPC company used Synopsys' Lynx Design System to standardise its flow and simplify migration to the next node.
Article  |  Topics: IP - Design Management, EDA - IC Implementation  |  Tags: , , ,   |  Organizations: ,
October 23, 2012
tdf-xilinx1-oct12-featim

Vivado, inside the new Xilinx design suite

The FPGA vendor's new flagship is now on public release. It adds an array of features, including support for system-level to HDL synthesis.
October 11, 2012
Tong Gao

The physical design challenges of 20nm processes

Manufacturability, routing, library design and more - it all needs rethinking at 20nm, writes Tong Gao of Synopsys.
Expert Insight  |  Topics: EDA - DFM  |  Tags: , , , ,   |  Organizations:
September 12, 2012
tdf-sept-SNPS-crit-tools-feat

Critical tools for 20nm design

A look at the way in which key tools, in IC implementation, modeling and extraction, and physical verification, are developing in response to the challenges of 20nm design
May 31, 2011

The Roadmap to LFD Value: Quantifying a Return on Investment in Calibre LFD

By the time a serious lithographic problem is identified at the fab, it is too late in the design process to make a simple layout change, resulting in a significant delay of the tapeout, and consequently chip delivery. To diminish the risk of sensitive layout structures, and avoid or reduce design delays, designers need the […]

Whitepaper  |  Topics: EDA - DFM  |  Tags: , , ,
June 1, 2010

Signoff-driven IC design

The demands of manufacturing closure at advanced process nodes make the traditional design-then-fix flow unmanageable. At 28nm and below, designers need a solution that can address manufacturing issues at any point in the design process, enabling a true correct-by-construction methodology. An effective solution must provide design-rule-check and design-for-manufacturing analysis using the actual foundry-approved signoff rules [...]
Article  |  Topics: EDA - DFM  |  Tags: , , ,

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