placement

Innovation is extending the technique's power across areas such as context-aware layout, accounting for multi-patterning and implementing fill.

FinFETs present a number of problems with respect to dynamic power consumption. Design techniques are being re-evaluated to deal with the issue.

Soft blocking to prevent cell spreading and other placement-optimization techniques helped improve power and clock speed on a Cortex-M7 test chip designed by ARM and Cadence.