PPA

January 27, 2022
Janet Attar is Product Marketing Manager at Siemens EDA responsible for Aprisa, Siemens’ place and route solution. She has over 15 years of experience in the semiconductor industry supporting various EDA tools in the digital space, including synthesis, place and route, signoff, and verification. Prior to Siemens, Janet was an Applications Engineer for Cadence Design Systems and a Physical Design Engineer for International Rectifier (now Infineon Technologies).

Aim for power first for best place-and-route results

The strategy of designing for best power rather than for best timing in place-and-route delivers better results all around.
Expert Insight  |  Topics: EDA - IC Implementation  |  Tags: , , ,
September 18, 2014

Using optimized design flows to meet PPA goals for SoC processor cores

How tuning a design flow can help optimize SoC processor cores for power, performance and area - and make it possible to do different optimisations for different cores on the same SoC.
September 2, 2014
Intel's trigate is among the structures to be modeled by the revised BSIM4

Design enablement and entitlement for 14/16nm finFET processes

How EDA tools are evolving to make it possible to design with finFET processes.
Article  |  Topics: EDA - IC Implementation  |  Tags: , , , ,   |  Organizations: , ,
August 27, 2014
Prasad Saggurti is the product marketing manager for embedded memory IP at Synopsys.

Six key criteria for deciding to migrate to a finFET process

Moving to a finFET process means considering process readiness, cost and yield, as well as the traditional power, performance and area advantages
Expert Insight  |  Topics: EDA - IC Implementation, IP - Selection  |  Tags: , ,   |  Organizations: , , , , ,

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