Aim for power first for best place-and-route results
The strategy of designing for best power rather than for best timing in place-and-route delivers better results all around.
PPA
Using optimized design flows to meet PPA goals for SoC processor cores
How tuning a design flow can help optimize SoC processor cores for power, performance and area - and make it possible to do different optimisations for different cores on the same SoC.
Design enablement and entitlement for 14/16nm finFET processes
How EDA tools are evolving to make it possible to design with finFET processes.
Six key criteria for deciding to migrate to a finFET process
Moving to a finFET process means considering process readiness, cost and yield, as well as the traditional power, performance and area advantages
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