HLS

Mentor's AI Accelerator Ecosystem adds reference designs, libraries and other forms of support around its Catapult HLS platform.

Mentor takes the wraps off new machine learning fueled features in its HLS and physical design families ahead of DAC 2019.

Mentor's technical conference will take place on May 2 at the Santa Clara Marriott and feature more than 45 user and vendor presentations.

Menta eFPGA IP is highly configurable making it well suited to the evolving designs that exploit HLS abstraction.

Tools that checks pre-synthesis C++ and SystemC code have historically had no understanding of hardware intent. The Catapult Design Checker fills that gap.