Blog Topics

In 2013, the Design Automation and Test in Europe (DATE) conference returns to Grenoble, France and with focus days on the Internet of Things and the cloud.

3D-IC integration techniques such as the use of TSVs, die stacking and interposers are unlikely to limit performance, according to research from TSMC and IBM

Altera has cut a deal with ARM to bring unified debug support to the FPGA fabric and Cortex-A9 processors inside the Cyclone SoC products, using a specialized version of ARM’s DS5 tool.

Intel has launched its first server SoC, based on a stripped-down Atom, in a bid to seal its place in microservers before ARM can ready its 64bit architecture for production. But the chip seems more a stake in the ground than the answer for low-power servers.

Can planar devices on fully depleted SOI resist the relentless rise of finFETs as the next device architecture of choice for the semiconductor industry? An evening panel at IEDM explored the trade-offs

Semiconductor process options outlined at IEDM by Luc van den Hove of imec as industry faces hard choices and rising costs

Mears Technologies and UC Berkeley describe at IEDM 2012 how oxygen in a silicon superlattice could boost performance beyond strained silicon at 14nm.

The modelling track at IEDM 2012 showed how germanium could be used in 14nm finFETs. Other work focused on tunnel FETs and analyzing MEMS using Spice.

Embedded software engineers need to focus on power optimization in their code much earlier and more comprehensively than many of them do today, says Mentor Graphics technologist Colin Walls.

Traditional IP reuse is giving way to configurable, customized cores delivered by semi-automated "IP factory" groups.