IP

Microsoft Azure aims to use royalty-free IP to build a more secure IoT and extend the reach of its cloud services.

Developing a security assurance standard for IP faces numerous problems but Accellera working-group members are trying to find an answer.

Cadence has developed a version of its Protium prototyping engine that supports larger designs and which is intended to go into data-center racks.

Achronix is introducing an FPGA architecture that pulls a full network-on-chip into the programmable-logic fabric combined with hardened matrix-math processors for AI.

Mentor is active across the program and its main and Verification Academy booths within the exhibition in Las Vegas.

EDA and IP supporters of the new event see the goal of greater integration with the electronic systems supply chain as fundamental to their involvement.

Accellera is trying to standardize extensions to UVM for mixed-signal design.

Large-scale MCMs and novel device architectures bookend the papers on machine learning at VLSI Symposia in an event that will also cover chiplet integration and other topics.

Synopsys and GLOBALFOUNDRIES are developing a portfolio of automotive IP for the chipmaker’s 22nm fully depleted silicon-on-insulator (22FDX) process.

Menta eFPGA IP is highly configurable making it well suited to the evolving designs that exploit HLS abstraction.