September 18, 2014
How tuning a design flow can help optimize SoC processor cores for power, performance and area - and make it possible to do different optimisations for different cores on the same SoC.
September 2, 2014
How EDA tools are evolving to make it possible to design with finFET processes.
August 29, 2014
EDA vendors and internal CAD teams use Verific parsers for tool development. Here's how one company developed its strategy for this popular technology.
August 27, 2014
Moving to a finFET process means considering process readiness, cost and yield, as well as the traditional power, performance and area advantages
August 7, 2014
FinFET and 3DIC technologies bring with them not just higher performance but an increased need for accurate parasitic analysis.
July 25, 2014
Altera uses standardized design flows to help integrate Intel foundry rules, cut time to tape-out - and speed the evolution of its design flows.
July 23, 2014
The 20nm node can offer power, performance and area advantages, but making these gains takes a deep understanding of the interactions between process and design.
July 13, 2014
Dynamic voltage and frequency scaling is effective for low-power VLSI design. Body or back bias can provide additional control over leakage and performance.
July 9, 2014
A change in the way the core compact models are developed has accelerated their development and, for the first time, allowed the models to be used not just for circuit simulation but to help guide process evolution as chipmakers play not only with materials but the shape of finFETs.
June 27, 2014
How to use PCIe in low-power SoCs by swapping the standard PCIe PHY for M-PCIe, defined by MIPI for mobile use
