May 8, 2017
Our extended fireside chat with Mentor Chairman and CEO Wally Rhines begins by canvassing his thoughts now the Siemens deal is done.
March 15, 2017
DVCon China general chair Andy Liu discusses Accellera’s new addition to its design and verification conference series (简体中文).
January 27, 2017
Richard Pugh looks at how innovations highlighted during the recent International Memory Workshop are driving the solid state drive (SSD) market.
December 9, 2016
Traditional techniques are being challenged by shortening design cycles and the effects of later process nodes.
December 2, 2016
Hierarchical signoff strategies for large SoCs at advanced nodes can be effective if sufficient attention is paid to reflecting the impact of cross-hierarchy parasitics.
November 29, 2016
FinFET processes and libraries are maturing, enabling designers to explore the best ways to take advantage of the capabilities of the new transistor design
October 3, 2016
Mentor's chairman and CEO has dug into why chip sales forecasts often miss the target and suggests some tools for assessing the Internet of Things.
October 3, 2016
Multi-patterning, finFETs and more are forcing more detailed overhauls of P&R software at each process node. We dig into some of the key new issues and how they are being addressed.
August 18, 2016
A look at how collaboration between design, process and tool development is becoming increasingly important to get the best out of the most advanced nodes.
June 1, 2016
By taking a pragmatic approach, the two technology giants have comfortably adopted high-level synthesis and verification - and have shared their experiences.