Learn how power-intent, LDEs, ESD and voltage-aware spacing techniques can particularly benefit from the use of static verification checks.
Static analysis offers a powerful way of identifying potential X-optimism problems before simulation. The article defines the issue and describes an established solution.
Traditional approaches do not catch all unknown state sources, lack capacity for big SoCs and mask bugs. Ascent XV addresses and overcomes these issues.
The argument for an integrated approach to SoC verification
View All Sponsors