June 25, 2021
Learn how to bring together your NLDM and CCS models to reach timing closure faster with Solido Analytics.
January 4, 2016
The 10nm process node calls for the use of SOCV techniques during timing signoff to avoid leaving too much performance on the table.
May 30, 2015
Clock-tree generation is coming under increased scrutiny because of its role in dynamic power consumption and problems caused by on-chip PVT variation.
May 19, 2014
The increased use of IP and a rise in process variability is driving a move to look at alternatives to traditional low-skew clock distribution strategies.
April 22, 2014
Mixed-signal chip designer Semtech on using Lynx Design System to manage multi-corner multi-mode sign-off when you've got 306 scenarios to check.
March 27, 2014
Using a physically aware flow to ensure that fixing one ECO doesn't introduce another during sign off.
December 23, 2013
How Marvell used an enhanced ECO tool flow for SoC design to cut overall time-to-timing-closure by nearly 70%.
September 6, 2013
Accounting for on-chip variation (OCV) has become a critical factor in assuring timing closure for nanometer-scale ICs and avoiding over-pessimistic margins.