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timing closure
Timing analysis shifts to statistical
The 10nm process node calls for the use of SOCV techniques during timing signoff to avoid leaving too much performance on the table.
Clock tree synthesis
Clock-tree generation is coming under increased scrutiny because of its role in dynamic power consumption and problems caused by on-chip PVT variation.
On-chip clock strategies and GALS
The increased use of IP and a rise in process variability is driving a move to look at alternatives to traditional low-skew clock distribution strategies.
Accelerating multi-corner multi-mode sign-off using the Lynx Design System
Mixed-signal chip designer Semtech on using Lynx Design System to manage multi-corner multi-mode sign-off when you've got 306 scenarios to check.
Achieving multi-scenario signoff quickly and predictably using timing-driven ECO
Using a physically aware flow to ensure that fixing one ECO doesn't introduce another during sign off.
Better management of timing closure and optimization
How Marvell used an enhanced ECO tool flow for SoC design to cut overall time-to-timing-closure by nearly 70%.
On-chip variation (OCV)
Accounting for on-chip variation (OCV) has become a critical factor in assuring timing closure for nanometer-scale ICs and avoiding over-pessimistic margins.
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