Siemens EDA

May 29, 2020
runtime monitoring featim

How to use runtime monitoring for automotive functional safety

The promise of autonomous vehicles is driving profound changes in the design and testing of automotive ICs.
May 26, 2020
cloud computing efficiencies with calibre for physical verification

How cloud computing is now delivering efficiencies for IC design

A Mentor-Microsoft-AMD pathfinder demonstrates the potential benefits of cloud-based physical verification.
May 7, 2020
CMP simulation dummy fill featured image

Keep chip designs on the level with CMP simulation and dummy fill optimization

This case study shows how rising CMP simulation quality can be leveraged to detect the position and type of planarity hotspots before manufacture and verify the planarity of a layout.
Article  |  Topics: EDA - DFM  |  Tags: , , ,   |  Organizations: ,
April 30, 2020
Scot Morrison Mentor

Delivering on security for Linux-based medical devices

How should you address the monitoring and resource challenges in maintaining security for Linux devices.
April 24, 2020
Ron Press is the technology enablement director of the Tessent product family at Mentor, A Siemens Business. He is a member of the International Test Conference (ITC) Steering Committee, a Golden Core member of the IEEE Computer Society, and a Senior Member of the IEEE.

How to gain a competitive edge with advanced DFT

Learn how the latest design for test innovations deliver efficiency and profitability across the design flow.
April 21, 2020
reset domain crossing featured image

How to achieve accurate reset domain crossing verification

The authors describe an emerging methodology based on a hierarchical data model approach that satisfies the key requirements for RDC verification.
April 14, 2020
Power ground check featim

How automated power/ground short checks slash time during implementation

Early detection using design integrity checks during implementation from abstract LEF/DEF inputs can deliver major efficiencies.
Article  |  Topics: EDA - IC Implementation, Verification  |  Tags: , , , , , , , , ,   |  Organizations:
March 30, 2020
Featured Image ESD feature

Automate P2P resistance checking for better, faster ESD protection

ESD has always been a major issue but with increasing densities and growing die sizes it is becoming a higher order concern. Automation and vizualization can help manage the task.
Article  |  Topics: EDA - DFM, IC Implementation  |  Tags: , ,   |  Organizations:
March 17, 2020
FeatIm P&R MaxLinear Mentor

How MaxLinear got faster signoff DRC while optimizing reliability and manufacturability

The RF and AMS specialist turned to design software that allowed it to run design checks during place and route.
February 28, 2020
SystemVerilog logo

Make it easier to exercise state machines with SystemVerilog

How the use of declarative, constraint-based descriptions can help you focus command sequences on areas of interest.
Article  |  Topics: EDA - Verification  |  Tags: , , , , ,   |  Organizations: ,

PLATINUM SPONSORS

Synopsys Cadence Design Systems Mentor - A Siemens Business
View All Sponsors