Because of the high analog content in memory designs, designers must understand how various effects impact reliability and performance.
Linking multiple disciplines, and fully accounting for networks and distributed functionality are vital to automotive E/E design.
Generating accurate ASIL metrics early in the functional safety lifecycle, reduces time-to-certification for ISO26262.
More optimistic about the semiconductor industries prospects than for some time, Siemens Joe Sawicki identified key EDA challenges at DAC.
Learn how Calibre 3D enables circuit and layout verification multi-die assemblies so that heterogeneous die processes can co-exist without significant impact to the deck.
Pre- and post-processing EDA techniques help streamline design rule checks and delivery efficient waivers to speed design and debug.
PIM memory boosts efficiency by operating on data without moving it to the CPU but realizing this type of novel technology posed power integration and planning challenges.
Innovation is extending the technique's power across areas such as context-aware layout, accounting for multi-patterning and implementing fill.
Delivering physical implementations at new process nodes is getting ever harder. Learn how to stay on track by checking work is rule-compliant as you go.
SiP promises advances in transmission speeds, bandwidth, accuracy and low power but verification requires careful evolution of existing tools.
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