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April 9, 2021
Spiral in on silicon bugs in six formal steps
The best paper winner at DVCon 2021 details a comprehensive methodology for making the best use of formal verification for bug hunting
Article | Topics:
EDA - Verification
| Tags:
bug hunt
,
debug
,
formal verification
,
methodology
| Organizations:
DVCon US
,
Siemens EDA
EDA Topics
DFM
DFT
ESL
IC Implementation
Verification
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