low-power verification

December 3, 2018
Rahul Chirania is a staff applications engineer with the static verification team at Synopsys.

Verifying clock domain crossings in UPF-based low-power SoCs

The verification challenges of using low-power design techniques to enable advanced power-management strategies in complex SoCs.
Expert Insight  |  Topics: EDA - Verification  |  Tags: , , , ,   |  Organizations:
October 8, 2015
Amol Herlekar, Synopsys

Preparing for low-power verification success: setting objectives and measuring outcomes

A look at what it takes to verify low-power SoC designs, including setting objectives and measuring outcomes in a UPF-driven verification strategy
Expert Insight  |  Topics: IP - Design Management, EDA - Verification  |  Tags: , ,   |  Organizations: ,

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