Learn how power-intent, LDEs, ESD and voltage-aware spacing techniques can particularly benefit from the use of static verification checks.
A look at some of the key techniques needed to ensue good code coverage during the verification of low-power SoC designs.
The verification challenges of using low-power design techniques to enable advanced power-management strategies in complex SoCs.
A look at what it takes to verify low-power SoC designs, including setting objectives and measuring outcomes in a UPF-driven verification strategy
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