An alphabet soup of AI, HPC, 5G and the IoT has finally seeded creation of a design infrastructure for silicon photonics.
High level synthesis (HLS) was adopted to realize innovative display IP as developed by a small core engineering team.
Pattern-based design/technology co-optimization (DTCO) estimates lithographic difficulty during the early stages of a new process technology node.
This introduction to the new Accellera standard includes a demo of portable stimulus in use to fully verify a DMA engine.
Techniques previously unavailable during ICE or testbench acceleration can now greatly speed emulation debug in those modes.
German consultancy E-Cooling describes its strategy for thermal and airflow analysis.
This second part looks at Mentor's views on flow neutrality, how DRS360 was born, machine learning and the threat from embedded Trojans.
Seven core considerations will help you realize your PCB for the Internet of Things more effectively.
Our extended fireside chat with Mentor Chairman and CEO Wally Rhines begins by canvassing his thoughts now the Siemens deal is done.
Hierarchical DFT is vital for large, complex designs. Users still to transition to the technique can nevertheless exploit its pattern reuse strategies as they move toward adoption.
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