How to achieve more accurate NAND soft-bit error injection
The article describes a pre-silicon strategy for the design and verification of SSD controllers that is faster and more flexible than ICE using physical NAND on a daughter-card.
Siemens EDA
Design space exploration finds hotspots during early process development
A new technique has been developed to catch potential new lithography issues when little design data is available for incoming nodes.
Three ways to lift productivity during physical verification
How to get the best PV results by reducing computational demands; handling data more efficiently and exploiting parallelization.
Improve custom/AMS design and productivity with in-design DRC
In-design DRC is a technique that frees up engineers from many of the challenges of delivering AMS design under ever more complex design rules.
Data-hungry applications demand emulation
Richard Pugh shows how the fast-growing market for drone silicon highlights emulation's power where high data volumes are critical.
Assessing the true cost of node transitions
John Ferguson reviews the key capital metrics you need to review when deciding whether to move to a new process.
Case study: Verifying and optimizing software for power on SoCs
How emulation was used to debug out-of-spec power on a multicore ARM design using the AXI bus.
Catch multi-patterning errors clearly at advanced nodes
How to address increasingly complex patterning issues and debug them efficiently as design moves toward 12 and 10nm.
How Channel Operating Margin helps Gigabit Ethernet PCB analysis
The COM methodology is being extended and more widely adopted across high-speed designs thanks to deeper tool integration.
Making security a profit center for silicon
The assumption has been that extra security eats into profit margins. But with some lateral thinking it can actually improve the bottom line.