Siemens EDA

June 18, 2018

Formal fault analysis for ISO 26262: Find faults before they find you

How to use formal fault pruning, injection and sequential equivalency checking to meet the FMEA analysis requirements of the functional safety standard.
June 11, 2018
Jay Jahangiri, Product Manager for Mentor, a Siemens Business

How emulation’s SoC and SoS advantages begin with transaction-based co-modeling

An introduction to how virtual emulation has fueled the application of co-modeling for complex design verification.
May 9, 2018

Extend formal property verification to protocol-driven datapaths

Learn how planning and upfront knowledge of the challenges ahead can open up what has seemed a challenging task.
Article  |  Topics: EDA - Verification  |  Tags: , ,   |  Organizations:
April 23, 2018
data validation featured image

The three critical data validation points in a design flow

Why design data integrity matters from cell design to tapeout. These techniques will help ensure your validation process is as comprehensive as possible.
Article  |  Topics: IP - Design Management, EDA - DFM, Verification  |  Tags: , , , , , , , ,   |  Organizations:
April 9, 2018

ISO 26262 – The Second Edition: what’s in it… and what isn’t

A new version of the automotive safety standard arrives later this year. Review the main updates and see how it will combine with the incoming SOTIF autonomous driving standard.
March 19, 2018
Dr Lauro Rizzatti is a verification consultant and industry expert on hardware emulation.

How hardware emulation helps drones take flight

In an exclusive interview, Lauro Rizzatti discusses the increasing verification challenges for drone SoCs with Bo Shen, founder of fabless specialist Artosyn.
Expert Insight  |  Topics: EDA - Verification  |  Tags: , , , , ,   |  Organizations: ,
March 9, 2018
Saunder Peng is a Senior Application Engineer with Mentor, a Siemens Business. He received his B.S degree in Electrical Engineering from the University of California at Los Angeles, and his M.S. in Electrical Engineering from Columbia University, New York.

A better way to merge design files for physical verification

Still using custom layout or place and route tools here? Ditch that time-consuming practice for a real database merge flow.
February 28, 2018

How to achieve more accurate NAND soft-bit error injection

The article describes a pre-silicon strategy for the design and verification of SSD controllers that is faster and more flexible than ICE using physical NAND on a daughter-card.
Article  |  Topics: EDA Topics, EDA - Verification  |  Tags: , , ,   |  Organizations:
February 1, 2018
Design space exploration feature

Design space exploration finds hotspots during early process development

A new technique has been developed to catch potential new lithography issues when little design data is available for incoming nodes.
January 15, 2018
Physical Verification Efficiencies - featured image

Three ways to lift productivity during physical verification

How to get the best PV results by reducing computational demands; handling data more efficiently and exploiting parallelization.
Article  |  Topics: EDA - DFM, Verification  |  Tags: , , , ,   |  Organizations:

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