Managing finFET variability issues without extending design times is key to extracting the most from the new processes, key players told a panel at the recent SNUG meeting in Santa Clara.
Xilinx aims to be first of the FPGA makers to produce 20nm devices, expecting to move to production samples for some products by the end of the year.
Xilinx and TSMC are forming a single engineering team to accelerate development of a family of finFET-based field programmable gate arrays (FPGAs).
Dr Chenming Hu joins Mentor CEO Wally Rhines and Xilinx SVP Victor Peng to keynote free day-long User2User in San Jose on April 25th, capping a full technical program.
Two vendors have announced early adopter software implementations of the new video compression standard that promises an up to 50% bandwidth cut against H.264.
Leading vendors and users spoke of the challenges in developing today's SoCs when faced with a plethora of prototyping techniques - and the challenges that remain.
National Instruments wants to shift the focus for many embedded systems designers away from hardware cost optimization towards graphical programming as a way of reducing the time it takes to get targets up, running and productive.
The advantages and challenges of 3D IC integration, as we add vertical functional integration options to the traditional planar integration brought by the progress of Moore's Law.
Xilinx says it has made the first public release of its Vivado Design Suite – the reworked design environment for its sub-40mn programmable-logic devices that is based more heavily on concepts from the custom-IC world than its existing ISE toolset.
Blue Pearl is building alliances to bring its timing analysis tools to more users.
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