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ARM and Synopsys both plan to make inroads to the internet of things with their IP strategies.

Taking place in Chelmsford, MA on 27 August, the conference will feature user-authored papers, tutorials, a designer expo and keynotes from Cadence and IBM.

A Japanese government-funded project has become the basis of a standard proposed by the Multicore Association that may provide a better way of supporting development for multicore systems.

Three companies have donated technology to Accellera designed to improve TLM 2.0 modeling work, focusing on interrupts, register control and memory maps.

Cadence Design Systems has rolled out a new version of Virtuoso that deals with the physical-implementation issues that arise in the sub-28nm nodes.

Xilinx aims to be first of the FPGA makers to produce 20nm devices, expecting to move to production samples for some products by the end of the year.

Real Intent has linked its key tools into Synopsys' VCS Verilog simulation and HDL Compiler tool flows.

To get others to adopt its GPU cores, Nvidia must quickly build partnerships with tool vendors and foundries that guarantee easy implementation.

Graphics chipmaker nVidia has said it plans to license as IP cores some of its technology in the hope of building up a customer base among other chipmakers and systems houses developing their own SoCs.

Design security is a major target for Microsemi’s update to its Igloo series of flash memory-based FPGAs, which add an ARM-oriented memory subsystem.