Real Intent updates X verification tool
Updated tool checks for correct design initialization, as well as managing X optimism and X pessimism at RTL or netlist level.
Archives
Distributor builds ECAD-MCAD links with free software
RS Components is now offering a solid-modelling tool to work with its free PCB design tool to provide easier access to 3D mechanical design.
SNUG heads to Austin next week
Synopsys user meet in Austin carries forward themes from Boston event.
Intel tips 14nm processor, Quark core and SoC licensing plans
In a keynote at the Intel Developer Forum, CEO Brian Krzanich said the company would start making 14nm processors by the year end and confirmed intel would license SoC designs to be fabbed by other companies.
Speed boost for Palladium emulators
Cadence Design Systems has upgraded its Palladium emulators to a maximum capacity of 2.3 billion gates and 50 per cent higher performance.
SoC design gets hierarchical test strategy, improved compression; system design gains end-to-end IJTAG integration strategy
Synopsys automates standards-based hierarchical test insertion and improves test compression for SoCs; Mentor teams with ScanWorks for system-wide IJTAG.
Real Intent CEO Prakash Narain on moving from RTL to SoC sign-off
Prakash Narain of Real Intent on SoC sign-off, static verification, interoperability, predictability, ROI and more.
Imagination gives WiFi better sync for audio
Imagination Technologies has developed an audio synchonization technology for WiFi networks that the company aims to license to consumer-audio chipmakers and OEMs.
SNUG Boston focuses on challenges of gigascale IC design
Meeting focuses on advanced tools and techniques for the rapid development of gigascale ICs.
ARM buys securable display controller
ARM has agreed to buy from Cadence Design Systems the display controller IP cores developed by recent acquisition Evatronix.