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Collaboration on DTCO offers IBM a better way to evaluate combinations of transistor architectures, materials and other process technology innovations using design metrics, before real wafers become available for physical experimentation.

Research institute Leti and low-volume wafer service CMP are cooperating on a project to let fabless chipmakers explore the use of non-volatile resistive RAMs in their designs.

Faster PHYs needed to shift vast amounts of data around giant data centres.

The rapid growth of interest in machine learning and artificial intelligence has prompted Synopsys to bring all its AI IP together in a microsite and brochure.

Mentor has untethered its Veloce platform online because it feels more designs need emulation and the cloud can now support it.

Research institute Leti and Soitec have decided to team up to work on a new generation of engineered substrates, such as specialized SOI wafers.

Accellera has published the first release of the Portable Test and Stimulus Standard (PSS), with tools suppliers following up with software support.

It’s the back-end that needs work as system-level considerations begin to dominate design, Qualcomm’s vice president of engineering said at DAC.

IoT device makers should play more with their software and make use of techniques used in website design to increase overall usability, Amazon’s head of IoT analytics has claimed.

Cadence Design Systems has made a collection of its tools suitable for cloud computing, providing them for both Cadence- and customer-managed environments.