Analyzer merges constraints for multiple timing modes

By Chris Edwards |  No Comments  |  Posted: June 7, 2016
Topics/Categories: Blog - EDA  |  Tags: , , , ,  | Organizations:

Ausdia has launched a product intended to reconcile the multiple sets of timing constraints needed for operating and test modes so that a consistent group of constraints can be fed to implementation tools.

Timevision ModeMerge takes multiple functional and test timing modes, each as a discrete SDC file, and merges them into a single SDC timing mode. This allows the timing behavior of multiple distinct modes to be represented as a single timing mode with a single SDC, so that place-and-route tools and static timing tools can optimize and verify the design in a single session.

The ModeMerge tool is designed to handle the many different types of test modes that are needed to deal with situations such as low- and high-speed capture, serial or parallel scan, built-in self-test (BIST), and memory test. The tool is meant to relieve SDC authors of the burden of trying to reduce the number of modes and their constraints manually.

In a growing number of cases, design teams have encountered “mode conflicts” where optimizing one mode impacts optimization in other modes, leading to non-convergent behavior in timing closure, Ausdia claims.

Ausdia says ModeMerge uses innovative technology to ensure accurate SDC merging across all possible SDC clock topologies, as well as accurate backtracking so that the source of all merged SDC data can be easily determined. The company claims the latest in SDC timing constructs are used to efficiently manage the timing behavior of the resulting mode and reduce runtime.

The runtime to merge a 3.3 million-instance design with 7 modes and 25 clocks per mode is less than 50 minutes and 21Gbyte of memory (including the time to load each timing mode), Ausdia says.

“We kept hearing from customers that other mode merge products were not able to merge all designs, or that they had a lot of restrictions on the types of SDC topologies that would be supported across modes. In addition, the runtimes of these tools often ran into one or two days, obliterating any advantage of using a mode merged SDC file,” said Ausdia president and CEO, Sam Appleton.

“Most design teams, and many SoC timing verification teams, have been trying to get all behavior represented inside a single session timing mode for faster closure and analysis without compromising accuracy. Now, we’re offering an advanced solution for optimizing place-and-route and timing closure on designs with more than one timing mode,” Appleton added.

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