Menta launches fourth-generation embedded FPGA core
Programmable-logic specialist Menta SAS has launched its fourth generation of embedded field-programmable gate array (FPGA), expanding support to several additional 28nm and 14nm process technologies.
The embedded FPGA core design now supports the TSMC 28nm HPM and STMicroelectronics 28nm FDSOI processes in addition to GlobalFoundries’ 14nm LPP process.
“Customers are trying to go early to market where they don’t have the full specification yet or the specification is still evolving,” said Yoan Dupret, business development director of Menta. “Or they are in the situation where they want to offer multiple variants.
“These technologies become more interesting when you decrease the node size, typically starting from 65nm. It starts to get interesting at 40nm because the evolution of nodes comes with the evolution of cost.”
The chief improvement with the fourth generation compared to its predecessor is to the way interconnect is used. Reducing the degrees of freedom to focus on the most common types of connection between lookup table blocks increased overall logic density – a key issue with embedded FPGAs.
Dupret claimed: “We increased the available logic inside and decreased area by 20 to 30 per cent. And we strongly improve our routing algorithm. Also static power has been divided by three.”
The embedded FPGA, which uses a volatile configuration cell architecture, employs standard cells for the programmable logic to ease porting and supports conventional scan chains for test. Dupret added. “We use standard cells only. Fault coverage is supported up to 99.8 per cent.”
Menta pre-defined eFPGAs have from 7k-60k equivalent ASIC gates, plus DSP blocks. The IP cores are delivered as hard macros with optimized arrays sizes. In addition, Menta can deliver custom IP cores with embedded logic blocks (eLB), embedded custom blocks (eCB), and embedded memory blocks (eMB), each of which are customizable in type, number and size to address various markets and applications. Menta also provides its own synthesis, mapping and place-and-route tool for implementing logic on the arrays.
