Blue Pearl is building alliances to bring its timing analysis tools to more users.
At last year’s DAC, leading EDA analyst Gary Smith said chip design had run into a big problem: it was already too expensive to be worthwhile for most companies. Soon afterwards, three companies rang to tell him that the figures were too pessimistic: it was not costing in the region of $75m but perhaps just […]
The troops will be out in force next week to claim progress on 20nm AMS design flows that take manufacturability into account.
If you're planning your DAC visit or want to set some Google Alerts for next week, it's time to consult the perennial touchstone.
But as it celebrates a decade of OpenAccess, the standards body also looks toward the future in PDKs, advanced DFM and 3D.
Atrenta is updating existing tools and planning new ones to help designers get the most bang for their joule.
Calypto has combined the Catapult high-level synthesis (HLS) tool with elements of its PowerPro software to focus on the demand for lower-power SoC designs.
French start-up and conference debutant joins the drive to ease partitioning for FPGA prototypes
UCIS 1.0 will provide a common format to analyze and compare data from different vendors' tools. Yup, it's a 'Biden' of a deal.
The partnership's 3.1 specification is open for review, with performance enhancements and alignment to Accellera's IP-XACT for metadata