clock domain crossing

September 30, 2014

Real Intent’s Meridian CDC flexes hierarchical muscle, adds flexible debug

Major overhaul of clock domain crossing suite adds configurable debugger, boosts performance by 30% and cuts memory 40% for 'giga-scale' designs.
Article  |  Topics: Verification  |  Tags: , ,   |  Organizations:
June 2, 2014

Real Intent’s Pranav Ashar on converging design and verification

Verify early and simulate as little as possible - the idea is familiar but how do you get there?
October 30, 2013

The prospects for GALS: Real Intent’s view

Real Intent CTO Pranav Ashar talks about GALS: the reasons for and against using asynchronous protocols for chip-crossing communications and what to do about verification.
Article  |  Topics: Blog - EDA  |  Tags: , , ,   |  Organizations:
September 5, 2013

Real Intent CEO Prakash Narain on moving from RTL to SoC sign-off

Prakash Narain of Real Intent on SoC sign-off, static verification, interoperability, predictability, ROI and more.
July 8, 2013

Real Intent links tools to Synopsys flows through in-Sync program

Real Intent has linked its key tools into Synopsys' VCS Verilog simulation and HDL Compiler tool flows.
Article  |  Topics: Product  |  Tags: , , ,   |  Organizations: ,
June 18, 2013

Real Intent highlights hierarchical clock domain crossing with Meridian 5.0

SystemVerilog and Synopsys Verdi integration are among further enhancements as clock domain crossing competition intensifies.
Article  |  Topics: Blog - EDA, - RTL, Verification  |  Tags: , ,   |  Organizations: ,
May 14, 2013

Real Intent-DeFacTo sign-off flow for RTL combines CDC and DFT

Real Intent and DeFacTo Technologies combine clock-domain crossing and design for test tools in RTL sign-off flow.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations: ,
October 17, 2012

Mentor extends Questa with formal coverage checks

New features provide enhanced formal checking analysis, code coverage closure and extended clock domain crossing analysis.

PLATINUM SPONSORS

Synopsys Cadence Design Systems Siemens EDA
View All Sponsors