Verify early and simulate as little as possible - the idea is familiar but how do you get there?
Real Intent CTO Pranav Ashar talks about GALS: the reasons for and against using asynchronous protocols for chip-crossing communications and what to do about verification.
Prakash Narain of Real Intent on SoC sign-off, static verification, interoperability, predictability, ROI and more.
Real Intent has linked its key tools into Synopsys' VCS Verilog simulation and HDL Compiler tool flows.
SystemVerilog and Synopsys Verdi integration are among further enhancements as clock domain crossing competition intensifies.
Real Intent and DeFacTo Technologies combine clock-domain crossing and design for test tools in RTL sign-off flow.
New features provide enhanced formal checking analysis, code coverage closure and extended clock domain crossing analysis.
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