Real Intent tackles CDC at the physical level
Meridian Physical CDC targets post-synthesis gate-level clock domain crossing issues, including unintended glitches and functional failures.
clock domain crossing
Real Intent’s Meridian CDC flexes hierarchical muscle, adds flexible debug
Major overhaul of clock domain crossing suite adds configurable debugger, boosts performance by 30% and cuts memory 40% for 'giga-scale' designs.
Real Intent’s Pranav Ashar on converging design and verification
Verify early and simulate as little as possible - the idea is familiar but how do you get there?
The prospects for GALS: Real Intent’s view
Real Intent CTO Pranav Ashar talks about GALS: the reasons for and against using asynchronous protocols for chip-crossing communications and what to do about verification.
Real Intent CEO Prakash Narain on moving from RTL to SoC sign-off
Prakash Narain of Real Intent on SoC sign-off, static verification, interoperability, predictability, ROI and more.
Real Intent links tools to Synopsys flows through in-Sync program
Real Intent has linked its key tools into Synopsys' VCS Verilog simulation and HDL Compiler tool flows.
Real Intent highlights hierarchical clock domain crossing with Meridian 5.0
SystemVerilog and Synopsys Verdi integration are among further enhancements as clock domain crossing competition intensifies.
Real Intent-DeFacTo sign-off flow for RTL combines CDC and DFT
Real Intent and DeFacTo Technologies combine clock-domain crossing and design for test tools in RTL sign-off flow.
Mentor extends Questa with formal coverage checks
New features provide enhanced formal checking analysis, code coverage closure and extended clock domain crossing analysis.
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