Mentor extends Questa with formal coverage checks
New features provide enhanced formal checking analysis, code coverage closure and extended clock domain crossing analysis.
Author Archives: Paul Dempsey
TSMC sketches finFET roadmap
16nm Pathfinder design kits next February and risk production from November 2013. Benchmarked to a 40% increase in speed, 50% reduction in power, and 60% reduction in area.
Tech Design Forum moves to new social media homes
Check out our new pages on Twitter, LinkedIn and Facebook
Event alert: TSMC Open Innovation Platform
With the foundry giant set to take the wraps off its latest flows and innovations in just seven days, remember that you must pre-register to attend its Silicon Valley event. Also here are some pre-event pointers.
Synopsys buys EVE and the death of dogma
The EDA giant fills out its prototyping and verification line-up with a long-mooted acquisition, and is set to become the first of the 'big three' to offer an in-house soup-to-nuts flow.
Aldec and Xilinx give ASIC prototyping another nudge
Four HES boards in sequence can handle designs up to 96 million gates.
CDN Live Beijing: Easing Sigrity into place
Anyone still tempted to regard PCB design as electronics’ sleepy backwater, obviously hasn’t been taking notice of trends not just in shrinking form factors but also I/O and memory standards. Proliferation not just in standards but in speeds have been creating whole new sets of challenges ranging from power and signal integrity right through to […]
CDN Live Beijing: ARM and the Middle Kingdom
It’s not that long since ARM was, to be blunt, rather fussy about the companies to which it licensed its technology – and at what level. Today, ‘ARM in a box’ comes in a number of flavors. Somewhat appropriately, the company linked with Cadence Design Systems and TSMC at the former’s recent CDNLive user conference […]
DAC 2012: Synopsys marries virtual and FPGA prototyping
Expose your transaction-level innovations to the real world early on and catch bugs before simulation.
DAC 2012 Interview: Mentor DFM chief Joe Sawicki on 20nm
The 20nm node will be making headlines at DAC. What are the challenges, what's being done about them and how could this work help engineers working at more mature nodes.