TSMC sketches finFET roadmap

By Paul Dempsey |  2 Comments  |  Posted: October 16, 2012
Topics/Categories: no topics assigned  |  Tags:

TSMC will put a 16nm finFET into risk production in November 2013 and release an initial development kit to customers next February. Current data benchmarks the TSMC finFET (Guide) against the foundry’s highest performance 28nm nanometer process (28HPM) and points to a 40% increase in speed, 50% reduction in power and 60% reduction in area.

Development within the TSMC ecosystem has started much earlier for finFET than for any other process – indeed such pre-research has been starting earlier and earlier for each successive node. Hence, the planned release of a customer kit even as 20nm and CoWoS only now come into play.

The 0.1 finFET PDK may also include pointers on co-development work TSMC has undertaken with ARM on the processor and IP company’s 64bit-enabled v8 architecture, expected to be unveiled at the end of this month.

TSMC also said that it expects to introduce a 10nm finFET in 2016.

The company has also taken the wraps off a Reference Flow for both its 20nm process and 2.5D silicon interposer CoWoS technology (Guide).

Meanwhile, the company also outlined more details on its Reference Flow for both its 20nm process and its 2.5DIC silicon interposer (Guide) technology, which it calls CoWoS, for chip-on-wafer-on-substrate.

With Reference Flow 20nm ready for download today, the company will introduce a high-k metal gate process next year, CLN20SOC, aimed as the name suggests at highly integrated designs.

All foundation IPs are already within the new flow alongside tools. Speciality IPs are being added over the period between Q4 2012 to Q1 2013.

One of the big claims in the 20nm flow though is that TSMC has validated the content to be double patterning ready but sought to make the need to undertake this tricky task almost transparent to the user.

Reference Flow CoWoS is also progressing solidly. The company has formalized and released the design kit, flow, IPs and undertaken internal validation. It is now ready to offer the interposer-based route to integration commercially.

The company reckons that supporting the technology contained within its design ecosystem now costs it and partners $1.5B a year. Both the EDA and IP segments of this have increased fourfold since 2008, as design and manufacturing complexity have burgeoned.

2 Responses to TSMC sketches finFET roadmap


Synopsys Cadence Design Systems Siemens EDA
View All Sponsors