Aldec and Xilinx give ASIC prototyping another nudge

By Paul Dempsey |  No Comments  |  Posted: September 17, 2012
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Aldec launches its HES-7 prototyping boards, with a pair of Xilinx Vertex-7 FPGAs on each. This gives them a standalone 24 million gate capacity, scaleable to 96 million by connecting up to four boards together.

“Today’s SoC/ASIC prototype teams are using off-the-shelf prototype boards that utilize large numbers of low density FPGAs. This makes implementing the SoC/ASIC design a painful process that requires more time-consuming design partitioning and added tool expense”, said Zibi Zalewski, Hardware Division General Manager at Aldec, “Using a dual chip HES-7 prototyping solution from Aldec together with Xilinx’s industry leading Virtex-7 2000T devices reduces the design implementation effort and lowers the tool expense when supporting multi-million gate SoC designs.”

That’s true up to a point, but there’s been a general drive towards pushing the capacity on FPGAs, particularly given that ASIC today often means SoC, and that means some fairly hefty levels of integration.

Perhaps more significant is that – and I’m ready for the inevitable correction here – this is the first prototyping solution outside Xilinx to use its Vivado software suite that was launched last Spring (and which we’ll be taking a more in depth review of in the next week or so).

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