Cadence expands Protium for rack-based prototyping
Cadence has developed a version of its Protium prototyping engine that supports larger designs and which is intended to go into data-center racks.
Author Archives: Chris Edwards
ESDesign West gets HoT
Heart of Technology (HoT) founder and Jim Hogan talks about the event at the upcoming ESDesign West show in San Francisco.
Achronix deploys network on chip for faster FPGAs
Achronix is introducing an FPGA architecture that pulls a full network-on-chip into the programmable-logic fabric combined with hardened matrix-math processors for AI.
Security, machine learning, and variety at DAC
Security and machine learning are two topics that take center stage at DAC this year, says the conference’s general chair Rob Aitken.
Formal engines learn from experience
Cadence and OneSpin are applying various forms of machine learning to their tools to automate formal verification.
May meeting to push for UVM analog extensions
Accellera is trying to standardize extensions to UVM for mixed-signal design.
Machine learning and chiplets headline VLSI Symposia
Large-scale MCMs and novel device architectures bookend the papers on machine learning at VLSI Symposia in an event that will also cover chiplet integration and other topics.
DAC announces first set of keynotes for 2019
Electronic musician Thomas Dolby will be among the keynote speakers at the 56th Design Automation Conference (DAC) in Las Vegas.
ODSA weighs options for chiplet interconnect
An Open Compute Project group working on multichip integration sees a combination of parallel and serial interfaces being important for interchip communication.
Cadence presents plan for piecemeal cloud compute
Cadence has launched a web-based EDA service the company hopes will ease the transition from self-hosted computing to more flexible cloud-based development.