A look under the hood of IC Compiler II, Synopsys' next-generation netlist-to-GDSII implementation system.
Soft blocking to prevent cell spreading and other placement-optimization techniques helped improve power and clock speed on a Cortex-M7 test chip designed by ARM and Cadence.
ARM and TSMC used an extensive pre-planning process, including a static analysis of each module's overall logic structure, to put together a 2.3GHz processor design based around ARM's main 64bit Big.Little pairing for the foundry's 16nm finFET process.
How tuning a design flow can help optimize SoC processor cores for power, performance and area - and make it possible to do different optimisations for different cores on the same SoC.
How EDA tools are evolving to make it possible to design with finFET processes.
EDA vendors and internal CAD teams use Verific parsers for tool development. Here's how one company developed its strategy for this popular technology.
Moving to a finFET process means considering process readiness, cost and yield, as well as the traditional power, performance and area advantages
FinFET and 3DIC technologies bring with them not just higher performance but an increased need for accurate parasitic analysis.
Altera uses standardized design flows to help integrate Intel foundry rules, cut time to tape-out - and speed the evolution of its design flows.
The 20nm node can offer power, performance and area advantages, but making these gains takes a deep understanding of the interactions between process and design.
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