The massive complexity of 5G and automotive systems and the need for advanced verification techniques set the scene for DVCon Europe this year.
DVCon Europe this year provides a venue for extending UVM, SystemC and TLM for faster, more effective verification its organizing committee claims.
Ahead of June's Design Automation Conference, Agnisys and Semifore have both released tools aimed at reducing the overhead of implementing register-rich SoCs.
Early registration has opened for the DVCon Europe conference to be held in Munich, Germany in November.
Technology from Duolog acquisition used to ease the configuration of interconnect, debug and trace - and the integration of third-party IP
Accellera has vendor extensions for IP-XACT that allow tool-specific metadata to be added to support activities such as power-aware verification and floorplanning.
Xilinx has created Vivado, a new set of tools to support sub-30nm FPGAs that, for advanced designs at least, will take over from its long-established ISE suite.
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