IP-Xact


September 22, 2017

5G and automotive provide applications focus for DVCon Europe

The massive complexity of 5G and automotive systems and the need for advanced verification techniques set the scene for DVCon Europe this year.
September 13, 2016

DVCon Europe to examine role of UVM, SystemC in system-level verification

DVCon Europe this year provides a venue for extending UVM, SystemC and TLM for faster, more effective verification its organizing committee claims.
Article  |  Topics: Blog - EDA, Embedded  |  Tags: , , , ,   |  Organizations:
May 25, 2016

Register tools appear ahead of DAC

Ahead of June's Design Automation Conference, Agnisys and Semifore have both released tools aimed at reducing the overhead of implementing register-rich SoCs.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , ,   |  Organizations: ,
September 2, 2015

Early registration opens for DVCon Europe 2015

Early registration has opened for the DVCon Europe conference to be held in Munich, Germany in November.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,   |  Organizations:
June 3, 2015

ARM eases interconnect, debug, third-party IP integration for SoCs

Technology from Duolog acquisition used to ease the configuration of interconnect, debug and trace - and the integration of third-party IP
Article  |  Topics: Blog Topics  |  Tags: , , ,   |  Organizations: ,
October 2, 2013

IP-XACT gets design-flow extensions

Accellera has vendor extensions for IP-XACT that allow tool-specific metadata to be added to support activities such as power-aware verification and floorplanning.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , , ,   |  Organizations:
April 24, 2012

Xilinx revamps design software for new processes

Xilinx has created Vivado, a new set of tools to support sub-30nm FPGAs that, for advanced designs at least, will take over from its long-established ISE suite.
Article  |  Topics: Commentary, Design to Silicon  |  Tags: , , , , , ,   |  Organizations:

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