February 26, 2019
Tools that checks pre-synthesis C++ and SystemC code have historically had no understanding of hardware intent. The Catapult Design Checker fills that gap.
February 22, 2019
OneSpin will focus at DVCon on its formal integrity verification platform for the RISC-V open-source which aims to speed up the core's adoption. The company will also feature the solution with a partner at EmbeddedWorld.
February 21, 2019
Metrics Technologies demonstrate its cloud-based platform for ASIC and complex FPGA verification and discuss a new partnership with Concept Engineering.
February 19, 2019
The company will demonstrate the latest capabilities in its Trek5 portfolio, building on Accellera's Portable Stimulus Standard.
February 19, 2019
The verification IP specialist is focusing on its new products for RISC-V verification and for emulation platforms next week in San Jose.
February 18, 2019
Testbench connections often depend on the virtual interface feature of SystemVerilog but other options - like abstract classes - can help.
February 11, 2019
DVCon USA is coming soon. Mentor's 2019 involvement includes a keynote from parent Siemens and a tutorial on managing your formal verification processes.
January 21, 2019
Data-centre networking chip goes through full-chip design rule checking and layout-versus-schematic signoff on TSMC's 16nm finFET process in a day.
January 21, 2019
Physical verification challenge of large SoCs on leading-edge processes detailed in video series
December 28, 2018
With PSS moving toward greater adoption, the Siemens vendor seems PSS-DSL as a winner in terms of conciseness and ease-of-adoption.