whiteboxing

February 18, 2019

How to optimize your testbench-to-DUT connections

Testbench connections often depend on the virtual interface feature of SystemVerilog but other options - like abstract classes - can help.

Article | Topics: Blog - EDA, - Tested Component to System, Verification | Tags: abstract classes, DUT, interface, SystemVerilog, testbench, Verilog, virtual interface, whiteboxing | Organizations: DVCon, Siemens EDA

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