Trek5 takes the Portable Stimulus Standard (PSS)-compliant software beyond test suite synthesis. Breker will demonstrate practical examples of how PSS can be applied to accelerate UVM coding for complex blocks and software-driven verification for large SoC designs.
Specific Trek5 applications featured during DVCon include:
- Adnan Hamid, Breker’s chief executive officer, will be a panelist on “Verification and Compliance in the Era of Open ISA – Is the Industry Ready to Address the Coming Tsunami of Innovation?” The panel will be held on Wednesday (February 27, Oak/Fir, 8:30am-9:30am).
- “Product Life Cycle of Interconnect Bus: A Portable Stimulus Methodology for Performance Modeling, Design Verification, and Post-Silicon Validation” will be presented by Gaurav Bhatnagar, staff engineer at Analog Devices. He will discuss a PSS methodology using Trek5 during the “Applications of the new Portable Stimulus Standard” session on Wednesday(February 27, Monterey/Carmel, 10:00am-12:00pm).
- Breker and Willamette HDL will run a workshop titled, “Using Portable Stimulus to Verify an ARMv8 Sub-System Integration on an SoC,” on Thursday (February 28, Pine, 1:00pm-2:30pm. It will include an overview of the Accellera PSS language and a detailed plan for verifying an ARMv8 sub-system integration using Trek5.
Breker’s Trek5 offers complete solutions across the verification spectrum, Portable Stimulus synthesis is being the first step. The tool suite includes TrekGen for PSS-based test suite synthesis, TrekUVM, TrekSoC and TrekSoC-Si deployment optimizers, TrekDebug for post-verification analysis, the TrekDesigner graphical entry tool and a range of TrekApps.
TrekGen, a fully functional and PSS-compliant synthesis tool generates tests from the Domain Specific Language (DSL) and C++ variants of the standard using advanced solvers. It allows path constraints and path coverage to be applied across standard scenario models and includes advanced procedural support for power users. TrekDesigner, a graphical entry tool, comes with TrekGen and includes pre-verification analysis capabilities for reachability, coverage and test inspection.
Trek5 has deployment optimizers for three flows: UVM, SDV and post-silicon. Designed to be portable across flows, they allow PSS-generated tests to be deployed directly into existing test environments with minimal additional effort.
These features reduce the need for users to write SystemVerilog and C code into their PSS models to generate testbench code.
TrekUVM optimizes complex sequences, coverage and scoreboards using test scheduling synthesis and other capabilities for existing UVM environments. It allows multi-threaded, synchronized sequence streams to be generated from a single, easy-to-understand, white-box scenario specification.
TrekSoC includes a hardware/software interface (HSI) that affords micro-kernel OS-like services to simplify bare-metal processor C tests. Also included are advanced memory allocation testing, TrekBox backdoor memory access and other capabilities. This enables multi-threaded processor C tests and I/O transactions to be generated for SoC designs without end-user integration effort. Simulation and emulation variants are included.
Diagnostic tests are supplied by TrekSoC-Si for post-fabricated silicon or FPGA prototyping systems that make use of the same verification scenario tests. TrekSoC-Si includes hardware access so that the same environment can be used as with the Trek verification solutions..
TrekDebug allows self-checking, multi-threaded tests to be monitored and debugged, along with full coverage analysis and design profiling and optimization. This solution accesses common signal-level debuggers, such as Synopsys’ Verdi, to accelerate the debug process.
TrekApps provide solutions to common verification tasks, including cache coherency, ARMv8 installation testing and power-management analysis with more to follow. They deliver configurable test environments without the need to understand the PSS languages.