How to optimize your testbench-to-DUT connections
The connection between your testbench and the design-under-test (DUT) is anaspect of verification planning that has perhaps received less attention than it deserves. A technical paper is available that aims to help engineers decide how to optimize those connections, based on the demands of their projects.
Author David Rich, a senior verification consultant at Mentor, argues that while there has been broad discussion of how techniques based around object-oriented programming (OOP), constrained-random verification and coverage-driven verification can be used within a SystemVerilog (SV) testbench, testbench-to-DUT connection implementations have usually fallen back on SV’s virtual interface mechanism.
There are however some underconsidered alternatives. One particular reason for investigating them, Rich says, is that virtual interfaces (VIs) become much harder to realize as designs grow in size: for example, keeping all the VI parameters in sync with interface instance parameters becomes more and more challenging.
More outreach to your testbench
In his paper, Rich reviews a range of alternatives and combinations, with the aim of prompting engineers to look at more options when preparing to connect the testbench.
His analysis gives greatest consideration to SV’s abstract classes. These are OOP-based programming concepts that define software interfaces. They are similar to VIs, but then add features such as inheritance and polymorphism.
As well as discussing the abstract classes concept, Rich also provides a detailed code example of its use in combination with the VI feature in the paper’s appendix.
Other issues he addresses include enablers for Whitebox Verification, which is becoming increasingly common for system-level projects. These include hierarchical references and SV’s ‘bind’ construct.
Rich also considers the testbench-to-DUT connection in respect of designs that raise particular issues such as bidirectional or tri-state buses, the need to race conditions and the handling of clocking blocks.
‘The Missing Link: The Testbench-to-DUT Connection’ can be downloaded at this link.
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