DVCon Europe initial technical program unveiled
DVCon Europe has published the technical program for its upcoming November conference in Munich, Germany.
Blog Topics
IP and software portfolio introduced to speed IoT development
Low-power IP and software portfolio includes security hardware, Bluetooth and ISB interfaces, configurable processors and sensor subsystems
Synopsys extends FPGA-based prototyping to 1.6bn ASIC gates
Synopsys updates its FPGA-based prototyping system to offer more capacity, higher speed, faster bring-up, better ROI
Menta aims for TSMC 28nm with embedded FPGA cores
Menta has launched a family of off-the-shelf IP cores aimed at TSMC’s 28nm processes to provide reconfigurability for SoCs.
Debug monitors look for deadlock
UltraSoC has added deadlock detection capabilities to its multicore onchip debug framework.
Early registration opens for DVCon Europe 2015
Early registration has opened for the DVCon Europe conference to be held in Munich, Germany in November.
Flow exploration key to finFET network processor implementation
Flow exploration helps designers establish best approach to advanced network processor implementation on Samsung finFET process
10nm flow reveals complexity of finFET design process
Collaboration between ARM, TSMC and Synopsys reveals challenges of 10nm finFET design flows.
Samsung applies early prediction and color management to 10nm plans
Rapid virtual prototyping and a metal stack that's more designer friendly are two of the ways in which Samsung aims to build up foundry market share for its 14nm and 10nm finFET processes.
USB Type-C IP to ease end users’ frustration
Synopsys delivers reconfigured PHY IP to support reversible USB Type-C connector.