Synopsys claims latest Design Compiler shrinks existing netlist area, leakage up to 10%
Uses improved logic optimisations and a new approach to meeting timing.
Blog Topics
Cadence to buy Forte and build out HLS offering
EDA giant cites high-level synthesis' move into the mainstream as driven by IP integration challenges in striking deal for the HLS market leader.
Capacity may force uptick in chip prices, says analyst
Chip pricing could see a significant uptick because of reduced investment in fab capacity, according to Future Horizons.
Power analyzer pulls in scope functions for energy-saving designs
Yokogawa has pulled together power meter and oscilloscope functions into a hybrid instrument for teams working to increasingly stringent energy-usage regulations.
Cadence updates Incisive with formal, CRV, wreal additions
Cadence's Incisive 13.2 verification environment includes new formal and constraints engines, X propagation checks, and further real-number model support.
Inside Secure to offer IP for mobile hardware vaults
Inside Secure has developed a set of certification-ready hardware IP modules that can be used stand-alone or in conjunction with ARM's TrustZone
TSMC hints at glass interposer for mobile SoCs
Glass may be the high frequency interposer option given silicon concerns about power and noise. TSMC adds another pathfinder to its 3D arsenal.
Qualcomm’s take on preserving Moore’s Law economics
Industry-wide innovation is required to make scaling cost-effective at 7nm, says Qualcomm's VP of Technology. Time for a fat, cholesterol and MSG-free diet.
Graphene gets a reality check
A leading researcher argues that graphene will not replace but complement silicon and thrive in specialist applications.
FinFETs’ III-V future promises sub-7nm, RF and opto CMOS
FinFETs for 7nm and below processes will be able to integrate high-mobility III-V materials despite being built on silicon processes, thanks to recent work by imec.