Blog Topics

The complexity of on-chip interconnect and the relentless growth in software size will drive the move to a four-stage verification process as well as the increased use of formal techniques to speed up SoC-level testing, Mentor Graphics verification specialist Mark Olen claimed at the Verification Futures conference.

Training company Doulos is working on a second version of its Easier UVM guidelines intended to speed up the process of getting a UVM testbench underway for new users.

Microchip Technology has become the latest company to use easy access to middleware to encourage embedded-systems developers to move over to its platform.

Cadence Design Systems uses parallelism in its Voltus tool to provide faster IR drop analysis and bridge static timing and IC-level power-integrity analysis.

Highway1 has opened up Spring applications for its incubation service for hardware startups: trying to overcome the gap between prototype and product.

Synopsys has launched the ARC HS family of configurable-processor cores, using superpipelining to target high-performance embedded applications.

Jasper Design Automation has developed a tool that analyzes RTL and gate-level HDL for hidden paths that may expose on-chip secure elements to hackers.

Dr Ron Black also discussed his experiences with the Internet of Things in a lively keynote at the GSA Memory+ Conference in Taipei

Oracle aims to reduce the incompatibilities between the two main embeddable versions of Java as the company tries to make the language the natural choice for IoT.

ARM is making its Mbed online development platform the cornerstone of its push into the internet of things (IoT), with Java as its preferred language.