Arm to let customers bolt instructions onto V8 processors

By Chris Edwards |  No Comments  |  Posted: October 8, 2019
Topics/Categories: Blog - EDA, IP  |  Tags: , , , , , , ,  | Organizations:

Arm has decided to allow custom instructions to be developed for a subset of its processor cores and has developed a mechanism lets SoC designers implement them without incurring support charges.

For years, although competitors such as MIPS decided to make it possible for customers to add custom instructions, Arm refused to implement the capability arguing that instruction-set and tools stability was its objective. That is changing to a limited degree with the decision to implement an extension mechanism for the V8-M architecture.

Tim Whitfield, vice president of the automotive and IoT line of business at Arm, said the first core to support instruction-set extensions is the Cortex-M33. “Existing licensees won’t have to pay extra to access this. You will see it on all our V8-M cores in the future.

“We acknowledge custom instructions aren’t new,” Whitfield added but he argued that target markets such as the IoT and augmented reality provide additional impetus for offering the facility. “They provide potentially a very power-efficient solution for implementing specific algorithms. But there is the problem of how to add them without breaking compilers and debuggers and of dealing with the potential for fragmentation. We think we have come up with an elegant solution to balance the fragmentation against the benefits you get from using them. There is no disruption to the software ecosystem.”

To support custom instructions without having to get involved with their integration or a large amount of additional support, Arm has designated a set of 16 opcodes that customers can use. Each is configured to load and store a predefined set of registers: some load data elements from a pair of registers and store the result to one or another. Whitfield said the mixture is intended to cover most cases. If the custom instructions for a project only need single register accesses, for example, they can have the logic simply ignore the second loaded value in a typical dual-load configuration if they are the only ones spare.

As the main target is single-issue Cortex-M processors, the instructions will stall the pipeline if they take longer than one cycle to complete. However, the expected targets are operations such as bit-field manipulations, trigonometric functions, and custom comparisons that are likely to complete in one cycle. More complex operations would probably still employ a coprocessor-based approach.

Whitfield said: “Customers create a small piece of logic that implements the custom operation and we take care of hooking that into the CPU pipeline. There’s no real chance of partners breaking the CPU. Using a predefined instruction space means we can use standard compilers.”

Whitfield said the custom instructions do not need to be shared with Arm though the company is looking at the possibility of creating libraries for extensions that multiple customers could use. As with most other extendible architectures, the instructions themselves would typically be called in a C or C++ program using intrinsics calls.

The company is looking also at bringing custom-instruction support to the V8-R and V8-A families though, given the focus of the V8-A the more likely target would be V8-R cores used in the storage-controller market where the custom instructions might be used to support search functions.

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