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January 23, 2018

Codasip updates processor-architecture tools

Codasip has launched the seventh generation of its Studio software for processor design and tuning, aiming to take advantage of the interest in RISC-V as a core instruction set for customized processors.
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January 5, 2018

Ceva dedicates hardware to deep learning

Ceva has developed its first processor architecture aimed squarely at deep learning.
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December 18, 2017

Third time lucky for iKettle security

IoT kettle maker changed its approach to bolster security, the company's CTO explained at the IoTSF conference in London.
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December 1, 2017

Workshop sees the RISC-V ecosystem expand

The RISC-V workshop in California at the end of November 2017 provided the opportunity for Western Digital to commit its own work on processors for internal use to the open-source architecture and for the ecosystem of off-the-shelf cores and tools to expand.
November 20, 2017

Maxim uses own PUF for low-cost crypto devices

Maxim has used its own mismatch-based PUF technology to support a new line of low-cost security devices.
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October 23, 2017

Arm plans secure reference architecture for Cortex-M

Arm is putting together a security framework that the company is assembling to support, at least initially, IoT devices based on the Cortex v8M architecture.
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October 19, 2017

Microsemi sets up RISC-V partner program

Microsemi has set up an ecosystem program around the RISC-V soft cores the company has designed for its FPGAs.
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October 17, 2017

Arm TechCon 2017 preview: Synopsys

Synopsys' line-up at next week's ARM TechCon includes joint presentations with Huawei and Nvidia.
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October 17, 2017

Arm TechCon 2017 preview: Mentor

Mentor will present seven papers during the ARMTech Con and a dedicated session, and exhibit at Booth #606.
October 16, 2017

Accellera updates SystemC library

Accellera has released a maintenance update to the SystemC core language library that addresses a number of issues that users have reported over the past three years.
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