Codasip has launched the seventh generation of its Studio software for processor design and tuning, aiming to take advantage of the interest in RISC-V as a core instruction set for customized processors.
Ceva has developed its first processor architecture aimed squarely at deep learning.
IoT kettle maker changed its approach to bolster security, the company's CTO explained at the IoTSF conference in London.
The RISC-V workshop in California at the end of November 2017 provided the opportunity for Western Digital to commit its own work on processors for internal use to the open-source architecture and for the ecosystem of off-the-shelf cores and tools to expand.
Maxim has used its own mismatch-based PUF technology to support a new line of low-cost security devices.
Arm is putting together a security framework that the company is assembling to support, at least initially, IoT devices based on the Cortex v8M architecture.
Microsemi has set up an ecosystem program around the RISC-V soft cores the company has designed for its FPGAs.
Synopsys' line-up at next week's ARM TechCon includes joint presentations with Huawei and Nvidia.
Mentor will present seven papers during the ARMTech Con and a dedicated session, and exhibit at Booth #606.
Accellera has released a maintenance update to the SystemC core language library that addresses a number of issues that users have reported over the past three years.
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