Siemens brings ReadyStart RTOS to RISC-V
Siemens has expanded its Nucleus ReadyStart program to the RISC-V architecture.
Embedded
Connected cars call for safety islands
A Siemens Tessent white papers examines the role of safety islands in advanced automotive systems.
How to meet formal embedded software guidance for medical devices
Vulnerabilities in connected healthcare products have led medical requlators to issue further security recommendations for their design and maintenance.
Xilinx retools Versal for high-end edge AI
Xilinx has reworked its Versal FPGA for edge-AI applications.
Would you prefer a hypervisor or a multicore framework?
Determining which embedded technique to adopt is more than just a question of what cores the system has.
Arm looks to explore new realms for security with v9
Arm aims to introduce a novel security model in its upcoming v9 architecture along with further extensions for AI.
OpenHW gets free simulator from Imperas
Imperas Software has released a free instruction set simulator that covers the OpenHW Group's implementations of the RISC-V processor architecture.
Hypervisors and frameworks in the multicore environment
At the recent Embedded World show and conference, Colin Walls of Siemens tackled the choices facing software developers working with multicore SoCs.
Embeddedworld 2021 Digital preview: Siemens Embedded
Following its rebranding from Mentor, the division will have a strong presence in the main program and across virtual roundtables at next week's online event.
Getting a RISC-V embedded toolchain in place
A new white paper reviews the history of the open-source platform and provides guidance on best practice development for embedded.
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