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Ceva has decided to include neural network, vector processing and customized instruction sets in an IP platform for 5G NR terminals.

Arm plans to use its cryptography cores and technology from its Simulity Labs acquisition to SIM-based security into IoT devices.

Slovenian startup Red Pitaya has added a front-end module and firmware to its FPGA-based StemLab board to create a customizable vector network analyzer (VNA) and RF tester.

By the middle of this year Arm intends to deliver a processor designed specifically for deep-learning pipelines in edge devices, to capitalize on a move away from cloud computing for image and voice recognition.

UltraSoC has released its first implementation of processor trace for cores based on the RISC-V instruction set.

Codasip has launched the seventh generation of its Studio software for processor design and tuning, aiming to take advantage of the interest in RISC-V as a core instruction set for customized processors.

Ceva has developed its first processor architecture aimed squarely at deep learning.

IoT kettle maker changed its approach to bolster security, the company's CTO explained at the IoTSF conference in London.

The RISC-V workshop in California at the end of November 2017 provided the opportunity for Western Digital to commit its own work on processors for internal use to the open-source architecture and for the ecosystem of off-the-shelf cores and tools to expand.

Maxim has used its own mismatch-based PUF technology to support a new line of low-cost security devices.