MPW service arrives for RRAM
Research institute Leti and low-volume wafer service CMP are cooperating on a project to let fabless chipmakers explore the use of non-volatile resistive RAMs in their designs.
EDA
Mentor as a maturing Siemens business: 2. Foundations
How are Siemens' internal investments in Mentor to fuel innovation and integration stacking up alongside the boost it has given for M&A?
Mentor as a maturing Siemens business: 1. Acquisitions
Mentor has added three companies since its acquisition a little over a year ago - and there's method to this buying spree.
HLS speeds up IP deployment at FotoNation
IP supplier FotoNation has decided to embrace the use of high-level synthesis in the creation of cores for smartphones and other high-integration, low-power systems.
Verification engineers embrace emulation for the shift left
In a panel session at June's DAC, Synopsys customers talked about some of the ways they make verification more efficient and bring technologies such as formal, emulation, and simulation together.
Why the time has come for cloud-based emulation
Mentor has untethered its Veloce platform online because it feels more designs need emulation and the cloud can now support it.
Embedded FPGAs start to take hold in SoC
The embedded FPGA is beginning to find a market, with communications leading the way but machine learning likely to drive further adoption.
With RF, power and MRAM, FD-SOI finds its role
FD-SOI is gradually building up a presence as a technology not just for low-power but RF and power integration.
Leti and Soitec partner for wafer development
Research institute Leti and Soitec have decided to team up to work on a new generation of engineered substrates, such as specialized SOI wafers.
Cloud makes hardware acceleration more accessible
After the moves by Cadence and Mentor, emulation in the cloud may only be the start of providing verification acceleration as a service.