Siemens’ Sawicki puts priority on scaling in processes, productivity and systems
More optimistic about the semiconductor industries prospects than for some time, Siemens Joe Sawicki identified key EDA challenges at DAC.
high-level synthesis (HLS)
High-level synthesis for AI: Part Two
How Chips&Media used HLS on the development of a computer vision IP block.
High-level synthesis for AI: Part One
The computational and algorithmic demands made by computer vision systems highlight HLS' value for AI system development.
How Google and Qualcomm exploit real world HLS and HLV
By taking a pragmatic approach, the two technology giants have comfortably adopted high-level synthesis and verification - and have shared their experiences.
The shape of system design and verification in 2016
2016 marks the 20th anniversary of the term Electronic System Level (ESL), introduced by Gary Smith in 1996. Where are we now? And how will developments this year push the frontiers of practical ESL design?
Linking high-level synthesis with formal verification
High-level synthesis provides a way to explore hardware architectures to come up with the most efficient implementation for a given situation. But it has taken time for verification techniques to catch up with the idea and ensure design and architecture match.
How high-level synthesis helps optimize low power designs – Part Two
Continuing our series on high-level synthesis (HLS) for low power design. Part Two details how HLS helps you make and evaluate architectural decisions.
How high-level synthesis helps optimize low power designs – Part One
Going inside HLS' basics shows how it can deliver power savings over 50% for some applications.
Vivado HLS/AutoESL: Agilent packet engine case study
How Xilinx' Vivado HLS enabled the creation of an in-fabric, processor-free UDP network packet engine
Three essential steps to SoC design and verification
An evolved ESL-to-RTL methodology flow addresses the ‘discipline gaps’ between software and hardware engineering by using three system level-based software-hardware verification steps. The strategy is already available in TSMC’s Reference Flow 12.
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