March 21, 2022
Automating executable specifications as they evolve can deliver major efficiencies.
January 27, 2022
Generating accurate ASIL metrics early in the functional safety lifecycle, reduces time-to-certification for ISO26262.
April 2, 2019
How Chips&Media used HLS on the development of a computer vision IP block.
February 18, 2016
Advances in RTL floorplanning help cut front-to-back-end iterations, speed synthesis by 10X and boast the capacity needed for today's designs.
September 30, 2014
Lint is no longer just about checking RTL code. It already incorporates functional verification within a three-stage analysis. Time to look again at a 'familiar' technology.
May 29, 2014
A static-analysis tool that checks for errors in HDL code, lint is becoming an increasingly important addition to simulation for RTL and SoC signoff.
April 9, 2013
The chipmaker used Calypto’s PowerPro to carry out power analysis of its latest core design at the RTL rather than at post-gate synthesis.
April 25, 2012
Richard Pugh reflects on efforts to cut through the tangle of cables and make emulation easier.
April 5, 2012
More than half of design companies claim to use ABV but many have yet to deploy full methodologies.