functional verification

September 10, 2019
Adnan Hamid is co-founder and CEO of Breker Verification Systems, and the inventor of its core technology. He has more than 20 years of experience in functional verification automation. He received his Bachelor of Science degree in Electrical Engineering and Computer Science from Princeton University, and an MBA from the University of Texas at Austin.

Using portable stimulus for automotive random error analysis

The Portable Stimulus Standard helps overcome many of the verification challenges inherent in the strict requirements of ISO 26262.
September 9, 2016

The inside track on emulation growth

Analysts say there is a $1B market on the horizon. We talk with Mentor's Jean-Marie Brunet about where such a number could come from.
January 26, 2016
Bus contention and floating bus issues featured image

Bus contention and floating busses: Catch them before simulation

Bus contention and floating busses are well defined issues and therefore excellent candidates for being addressed with early-stage formal verification.
Article  |  Topics: EDA - Verification  |  Tags: , , , ,   |  Organizations:
November 2, 2015

How to cut verification time with VIP

This article shows practical ways to use verification IP for greater productivity with specific code examples from Mentor Graphics' Questa platform.
Article  |  Topics: EDA - Verification  |  Tags: , , , ,   |  Organizations: ,
May 29, 2015
Mentor Graphics/Wilson Research Group Functional Verification Study

Smaller designs face greater risk of respins

Research study suggests the maturity of your verification flow determines the likelihood of first-pass success far more than the complexity inherent in design size.
January 20, 2015
Veloce2 emulator

Assertion-based emulation

Combining assertion-based verification techniques with emulation makes for easier debug, better coverage and greater functional efficiency.
September 30, 2014
Pranav Ashar

The evolution of lint

Lint is no longer just about checking RTL code. It already incorporates functional verification within a three-stage analysis. Time to look again at a 'familiar' technology.
Expert Insight  |  Topics: EDA - Verification  |  Tags: , , ,   |  Organizations:
October 26, 2012

Emulation delivers system-level power verification

Overcome the time and visibility limitations of simulation and of gate-level and RTL-based strategies to achieve full-chip analysis.
Article  |  Topics: EDA Topics, EDA - ESL, Verification  |  Tags: , , , ,   |  Organizations:
August 23, 2012
Pranav Ashar

Verification challenges require surgical precision

The verification challenge is best addressed by a combination of highly targeted tools, according to Pranav Ashar, CTO of Real Intent.
Expert Insight  |  Topics: EDA - Verification  |  Tags: , , , ,   |  Organizations:
May 28, 2012

Emulation

The value of the emulation market has almost doubled in the last four years as the technique becomes increasingly valuable to hardware/software co-verification.

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