January 13, 2022
More optimistic about the semiconductor industries prospects than for some time, Siemens Joe Sawicki identified key EDA challenges at DAC.
February 20, 2020
How can we refine our approach functional verification to deal with the increasing number of systems that leverage artificial intelligence.
September 10, 2019
The Portable Stimulus Standard helps overcome many of the verification challenges inherent in the strict requirements of ISO 26262.
September 9, 2016
Analysts say there is a $1B market on the horizon. We talk with Mentor's Jean-Marie Brunet about where such a number could come from.
January 26, 2016
Bus contention and floating busses are well defined issues and therefore excellent candidates for being addressed with early-stage formal verification.
November 2, 2015
This article shows practical ways to use verification IP for greater productivity with specific code examples from Mentor Graphics' Questa platform.
May 29, 2015
Research study suggests the maturity of your verification flow determines the likelihood of first-pass success far more than the complexity inherent in design size.
January 20, 2015
Combining assertion-based verification techniques with emulation makes for easier debug, better coverage and greater functional efficiency.
September 30, 2014
Lint is no longer just about checking RTL code. It already incorporates functional verification within a three-stage analysis. Time to look again at a 'familiar' technology.
October 26, 2012
Overcome the time and visibility limitations of simulation and of gate-level and RTL-based strategies to achieve full-chip analysis.