Foundry

Moving to a finFET process means considering process readiness, cost and yield, as well as the traditional power, performance and area advantages

A change in the way the core compact models are developed has accelerated their development and, for the first time, allowed the models to be used not just for circuit simulation but to help guide process evolution as chipmakers play not only with materials but the shape of finFETs.

A panel session at DAC 2014 focused on the problems of high-speed, board-level interconnect and the roles of codesign and power integrity in solving them.

The encryption chain for today's highly collaborative designs needs to be managed with care.

What ARM learnt when it ran a Mali GPU-based test chip through a Synopsys tool flow onto a TSMC 20nm process

3D-IC design is ready for take-off, following several years of intense collaboration to develop the necessary tools, methodologies and flows

You can waive some physical verification errors related to legacy IP found in foundry DRC checks. Knowing which has involved lengthy manual analysis. TSMC is enhancing the process with automation.

Current shortages could switch in key markets by the end of the year.

We quiz TSMC’s Tom Quan on the latest methodological challenges being addressed by the world’s largest foundry’s signature Reference Flow.

Morris Chang was in on the ground floor of IC innovation at TI and remains there today as chairman of TSMC. Paul Dempsey reports.