flash

March 1, 2016

Mentor builds out verification IP for memory

About 1,600 new UVM System Verilog verification IP memory models will cut testbench development time and offer more time to increase coverage.
September 30, 2015

Vertical structures to debut at IEDM 2015

A novel approach to 3D NAND will be among the presentations at the International Electron Device Meeting to be held in Washington, DC in December.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , , ,   |  Organizations:
September 30, 2014

Altera moves to 55nm for non-volatile programmable logic

Altera has moved to a 55nm embedded flash process to continue its Max series of non-volatile FPGAs.
Article  |  Topics: Blog - Embedded, PCB  |  Tags: , , ,   |  Organizations:
September 29, 2014

TSMC adds sub-micron low-leakage processes

TSMC has launched three processes the foundry is aiming at internet-of-things (IoT) and wearable-device designs, providing lower-leakage versions of its 55nm, 40nm and 28nm processes.
Article  |  Topics: Blog Topics  |  Tags: , , , , , ,   |  Organizations: , ,
February 27, 2014

Filesystem streamlines flash usage for smart meters

HCC Embedded has developed a specialised filesystem for smart meters designed to reduce power consumption and increase flash memory lifetime.
April 29, 2013

GlobalFoundries to take Infineon flash to 40nm for MCUs

Globalfoundries will port Infineon Technologies’ flash technology to 40nm to support the manufacture of automotive and security microcontrollers (MCUs).
Article  |  Topics: Blog Topics  |  Tags: , , , ,   |  Organizations: ,
February 8, 2012

ITRS update goes online

The wait is over for the latest edition of the International Technology Roadmap for Semiconductors (ITRS).
Article  |  Topics: Commentary, Blog - EDA  |  Tags: , , ,

PLATINUM SPONSORS

Synopsys Cadence Design Systems Siemens EDA
View All Sponsors