ADC design shifts gears for lower power

By Chris Edwards |  1 Comment  |  Posted: March 20, 2014
Topics/Categories: Blog - EDA, IP  |  Tags: , , , , ,  | Organizations:

The successive-approximation (SAR) analog-to-digital converter (ADC) is not renowned for high speed. But advances in process technology have turned it from an architecture used mainly in industrial automation to a promising candidate for low-power ADCs on consumer communications devices, as S3 Group’s engineers found when designing an architecture for LTE-capable devices.

S3’s SAR ADC runs at sample rates up to 160Msample/s, taking it further into the domain normally associated with pipelined and flash ADCs. For the ADC, S3 claims an efficiency of 31fJ/conversion using the standard energy figure of merit and consumes less than 0.1mm2 of die space when implemented on a 40nm process.

Although the energy contribution of an ADC in a handset may not initially seem that large, Darren Hobbs, director of product management at S3, said the move from a pipelined architecture to this SAR implementation, which provides more than a tenfold increase in efficiency, will provide five to seven minutes of additional download time on LTE.

“The approach we’ve been using has been based on pipelined architectures,” said Hobbs. “With SAR-based designs you typically run into latency issues. But at 65nm and below, latency becomes less of an issue. What the SAR architecture gives you is something that is a lot smaller and a lot lower in power as well.”

Digital assistance

The move from pipelined to SAR at high speed is not entirely straightforward. “The capacitors are critical components and reach the point where the values being used become very similar to those of parasitics,” said Hobbs. “That involves extra complexity such as calibration circuitry.”

However, the additional digital support logic favors implementation on nanometer-scale processes and the company is working to port that down to 20nm-class processes for further savings. Initial work on finFET processes indicates that the SAR architecture should map across to those.

“That’s the beauty of the architecture. You can scale rapidly because of the large amount of digital content,” Hobbs claimed.

Although leading-edge process nodes support the high frequencies needed to implement SAR ADCs with bandwidths in the 100MHz range, those clock rates limit how far the architecture can go. Hobbs said there is potential to use the ADC design for infrastructure applications by interleaving multiple converters. The energy and die-area savings made possible by the shift to an SAR-based would help such a design compete with the the pipelined and flash architectures more commonly used in that domain.

IoT focus for SAR

The growth in interest in the Internet of Things (IoT) is leading to further developments in SAR ADCs for ultralow-power systems. Charge-redistribution architectures, which comprise a capacitor array, comparator and digital logic look to be good candidates. Late last year, researchers at the University of Navarra in Spain described a design that used optimizations in the way that the capacitors in a SAR ADC are switched to reduce the power per conversion.

“We changed the way the capacitors are switched in this kind of ADC, so that the voltage variations of the capacitors that are switched is much lower. This decreases significantly the energy required to switch them,” said Professor Antonio López-Martín of the University of Navarra.

López-Martín said the design is based on a comparatively old process technology – 0.5µm and operating at a voltage of 1.5V. This results in an energy figure of merit of around 80fJ/conversion. “The circuit could be translated to deep-submicron processes for even lower power as the supply voltage can be decreased,” said López-Martin.

For a design described at ISSCC earlier this year, researchers from the Massachusetts Institute of Technology (MIT) were able to improve energy efficiency by a further factor of ten through the use of predictive techniques.

Small changes mean lower energy

MIT researcher Frank Yaul said: “With a 0.6V supply voltage, this ADC has a maximum sample rate of 16 kS/s, with a figure-of-merit range of 3.5 fJ in the best case and 20 fJ in the worst case.”

The variation is due to the novel algorithm used by the SAR ADC. “The algorithm presented in the paper is called LSB-first Successive Approximation because we begin our SAR search with an initial guess simply equal to the value of the previous sample,” Yaul explained. “Then, instead of taking an MSB-sized step first, we take successively larger steps from the LSB upwards. Our assumption is that the input signal has low mean rate of change, so it is likely that the current sample is close in value to the previous one. By taking LSB-sized steps first, we can save power by reducing the number of bit cycles used to complete the conversion.”

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